The present invention broadly relates to integrated circuits, especially MOS buffer drivers, and deals more particularly with an improved circuit structure for protecting the buffer driver from electrostatic discharge (ESD).
Integrated circuits (ICs) may be damaged by electrostatic discharge (ESD) phenomena produced by any of a number of sources. One major source of ESD exposure to ICs is from the human body. A charge can be induced on a body capacitance of 150 pF, leading to electrostatic potentials of 4 kV or greater. Contact with a charged human body by an uncharged or grounded IC pin can result in a discharge for about 100 ns with the currents of several amperes. Similar levels of ESD may be imposed on IC""s from other sources such as from metallic objects and the so-called charged device model (CDM) wherein the IC itself is charged and discharged to ground.
As the density of very large scale integrated circuits (VLSI) circuit increases, the components of the circuits are becoming progressively smaller, and more susceptible to damage from ESD. For example, the gate oxides of MOS transistors are becoming thinner and thinner, thus making the gate oxide layer more susceptible to destruction caused by ESD. It is especially important to protect gate oxide at input buffers and to MOS components at bi-directional buffers and output drivers. In some cases, it is possible to use on-chip protection circuits dedicated to protecting internal IC circuitry from the effects of ESD, however, these special protection circuits add to the cost of the IC and may not completely eliminate the problem in many applications.
A unique problem of ESD protection is presented by I/O drivers having multiple stages of driver circuits that are selectable to achieve a particular I/O current level. In those cases wherein less than all of the total number of available stages is actually connected to achieve an output drive current, the remaining, unconnected stages are unused and are sometimes referred to as xe2x80x9cdummyxe2x80x9d output stages. Where an I/O driver possesses both active and dummy stages, an unbalanced or unsymmetric load situation arises when the I/O buffer is subjected to ESD. The active stages are connected to ground and thus have gate oxide layers that break down at a slower speed but at a higher voltage. Conversely the dummy stages are not connected to ground and their gate oxides breakdown more quickly but at lower voltage levels. As a result, an ESD current flowing through the IC is not evenly divided between the active and dummy stages. Consequently, the maximum ESD tolerance of the IC is determined by the most susceptible section, i.e. the active stages which have a lower breakdown voltage.
The task of designing IC""s to maximize their tolerance to ESD is complicated by the fact that design modifications to make the circuit more tolerant of ESD cannot be at the sacrifice of circuit performance. Thus, IC""s must be designed to tolerate industry standard levels of ESD, e.g. 2 kV without any reductions in specified levels of I/O driver currents.
The present invention overcomes the deficiencies of the prior art discussed above and satisfies the need for an improved ESD tolerant IC.
The present invention provides a novel structure for an MOS integrated circuit that improves the IC""s ability to resist damage caused by electrostatic discharge (ESD), where the IC employs both active and inactive sections of drivers.
In accordance with the present invention, an MOS integrated circuit includes first and second sections of MOS drivers, wherein the first section is connected to drive an output load at a desired level of current, and the second section comprises inactive, unused drivers. The drivers in both sections are defined by a plurality of multi-fingered channels of semiconductor forming the gates of the drivers. Because the gates of the unused section of the drivers are not connected to the output load, the amount of ESD current flowing through the unused drivers is greater than that flowing through the active drivers used to drive the load. In accordance with the present invention, the width and length of the channels forming the drivers in the first, active section are greater than those of the channels in the second, unused section in order to increase the ability of the drivers in the first section to carry the flow of current therethrough produced by an ESD.
In a preferred embodiment of the invention, the width and length of the channels defining the drivers in the first, active section are approximately twice the length and width of the channels forming the drivers in the second, unused section. In one embodiment, the total width of the channels defining the drivers in both the first and second sections is approximately 300 microns.
Accordingly, it is the primary object of the invention to provide an MOS integrated circuit having improved tolerance of electrostatic discharge, without damage.
Another object of the present invention is to provide an MOS integrated circuit as mentioned above which achieves higher resistance to ESD, without degrading normal circuit performance.
A still further object to the invention is to provide an input/output buffer with active and inactive sections that exhibits improved resistance to ESD without the need for special protective circuitry.
These, and further objects and advantages will be made clear or will become apparent during the course of the following description of a preferred embodiment of the invention.